NXP Semiconductors /LPC43xx /CREG /FLASHCFGB

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Interpret as FLASHCFGB

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED0 (1_BASE_M4_CLK_CLOCK)FLASHTIM 0RESERVED0 (POWER_DOWN)POW

POW=POWER_DOWN, FLASHTIM=1_BASE_M4_CLK_CLOCK

Description

Flash accelerator configuration register for flash bank B

Fields

RESERVED

Reserved. Do not change these bits from the reset value.

FLASHTIM

Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.

0 (1_BASE_M4_CLK_CLOCK): 1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz.

1 (2_BASE_M4_CLK_CLOCKS): 2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz.

2 (3_BASE_M4_CLK_CLOCKS): 3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz.

3 (4_BASE_M4_CLK_CLOCKS): 4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz.

4 (5_BASE_M4_CLK_CLOCKS): 5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz.

5 (6_BASE_M4_CLK_CLOCKS): 6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz.

6 (7_BASE_M4_CLK_CLOCKS): 7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz.

7 (8_BASE_M4_CLK_CLOCKS): 8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz.

8 (9_BASE_M4_CLK_CLOCKS): 9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz.

9 (10_BASE_M4_CLK_CLOCK): 10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions.

RESERVED

Reserved. Write zeros only to these bits.

POW

Flash bank A power control

0 (POWER_DOWN): Power-down

1 (ACTIVE): Active (Default)

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